Conventionally, an analog to digital converter (referred as A/D converter hereafter) is used in many fields. In particular, an A/D converter having a delta-sigma modulation type quantizer (referred to as .DELTA.-.SIGMA. modulation type quantizer hereafter) is widely used, because the .DELTA.-.SIGMA. modulation type quantizer has excellent aspects for reducing quantization noise, making a circuit into a Large Scale Integration (LSI) circuit or increasing the operational speed of circuits. Such an A/D converter with the .DELTA.-.SIGMA. modulation type quantizer will be referred to as .DELTA.-.SIGMA. modulation A/D converter hereafter.
Referring now to FIGS. 1 and 2, two examples of conventional .DELTA.-.SIGMA. modulation A/D converters will be described. One example of the .DELTA.-.SIGMA. modulation A/D converter has a typical construction of .DELTA.-.SIGMA. modulation type quantizers. Another example of the .DELTA.-.SIGMA. modulation A/D converter has an improved construction of the .DELTA.-.SIGMA. modulation type quantizers, as described later.
FIG. 1 shows a block diagram of the former conventional .DELTA.-.SIGMA. modulation A/D converter. This conventional .DELTA.-.SIGMA. modulation A/D converter comprises a .DELTA.-.SIGMA. modulation type quantizer 10 and a decimation filter 12. The .DELTA.-.SIGMA. modulation type quantizer 10 is constructed in, for example, a double-integration quantizer configuration. In such a double-integration quantizer configuration, the .DELTA.-.SIGMA. modulation type quantizer 10 comprises first and second adders 14 and 16. First and second integrators 18 and 20 and a quantizer 22. The first adder 14 is coupled to an input circuit 24 for receiving an analog input signal Sa to be digitalized. The quantizer 22 is coupled to an output circuit 26 through the decimation filter 12.
The first adder 14 combines the analog input signal Sa and a signal Sb. The signal Sb is fed back from the quantizer 22, as described later. The analog input signal Sa is applied to a non-inverse phase input terminal of the first adder 14. On the other hand, the feedback signal Sb is applied to its inversed phase input terminal. Thus, the feedback signal Sb is fed back in the well-known negative phase configuration.
A signal Sc output from the first adder 14 is applied to the frist integrator 18. The first integrator 18 integrates the signal Sc obtained from the first adder 14. A first integrated signal Sd output from the first integrator 18 is applied to the second adder 16. The second adder 16 combines the first integrated signal Sd and again the feedback signal Sb. The first integrated signal Sd is applied to a non-inverse phase input terminal of the second adder 16. On the other hand, the feedback signal Sb is applied to its inverse phase input terminal. Thus, the feedback signal Sb is fed back in the negative phase configuration.
A signal Se output from the second adder 16 is then applied to the second integrator 20. The second integrator 20 integrates the signal Se obtained from the second adder 16. A second integrated signal Sf output from the second integrator 20 is applied to the quantizer 22. The quantizer 22 carries out a quantization operation for the second integrated signal Sf.
The quantization operation by the quantizer 22 is carried out as follows. The quantizer 22 compares the second integrated signal Sf with a prescribed reference potential in every cycle of a clock signal CK. The clock signal CK is generated by a clock signal generator 28. The clock signal generator 28 generates the clock signal CK with a prescribed stable frequency Fc. The clock signal CK is supplied to the quantizer 22 as a sampling signal. The clock signal CK is further supplied to the decimation filter 12, as described later. The frequency Fc of the clock signal CK is set to a frequency sufficiently higher than the highest frequency component of the analog input signal Sa. Thus, the second integrated signal Se output from the second integrator 20 is sampled at a rate of the frequency Fc of the clock signal CK in the quantizer 22. Thus, a quantized signal Sg is output from the quantizer 22.
The quantized signal Sg obtained by the quantizer 22 is fed back to the first and second adders 14 and 16. Thus, the feedback signal Sb coincides with the quantized signal Sg output from the quantizer 22. the quantized signal Sg is integrated, re-sampled and again integrated to reduce quantizing noises occuring in the quantization operation by the quantizer 22 so that the quantization quality of the quantized signal Sg is increased. The quantized signal Sg output from the .DELTA.-.SIGMA. modulation type quantizer 10 is applied to the decimation filter 12. The decimation filter 12 thins out prescribed quantization data from the quantized signal Sg so that a digital signal Sh corresponding to the analog input signal Sa is obtained through the output circuit 26. The data decimation operation of the decimation filter 12 is carried out under the control of the clock signal CK supplied from the clock signal generator 28.
The former conventional .DELTA.-.SIGMA. modulation A/D converter having such a typical .DELTA.-.SIGMA. modulation type quantizer can carry out and A/D conversion with good quantizing accuracy and good quantizint noise reduction characteristic by a simple construction. However, recently reduction of quantizing noises to a greater degree has been desired. Thus, an improvement of the .DELTA.-.SIGMA. modulation type quantizer has been made by applying a dither signal to the analog input signal. Such an improved .DELTA.-.SIGMA. modulation type quantizer appears in the article "A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping", on pp. 921-929 of "IEEE Journal of Solid-State Circuits", Vol. SC-22, No. 6.
FIG. 2 shows a block diagram of the latter conventional A/D converter having such an improved .DELTA.-.SIGMA. modulation type quantizer. This conventional .DELTA.-.SIGMA. modulation A/D converter basically comprises a .DELTA.-.SIGMA. modulation type quantizer similar to the circuit of FIG. 8 in the article. In the following explanation of FIG. 2, reference numerals or letters used in FIG. 1 will be used to designate like or equivalent elements for simplicity of explanation.
As shown in FIG. 2, this latter conventional .DELTA.-.SIGMA. modulation A/D converter comprises third, fourth and fifth adders 30, 32 and 34, a dither signal generator 36, first and second .DELTA.-.SIGMA. modulation type quantizer 10a and 10b, an overflow prevention filter 38, a decimation filter 12 and a clock signal generation 28. Each block of the first and second .DELTA.-.SIGMA. modulation type quantizer 10a and 10b has a typical construction similar to the .DELTA.-.SIGMA. modulation type quantizer 10 of FIG. 1. The decimation filter 12 corresponds to the decimation filter 12 of FIG. 1. The clock signal generator 28 supplies a clock signal CK to the first and second .DELTA.-.SIGMA. modulaton type quantizer 10a and 10b and the decimation filter 12 as a sampling signal. The clock signal generator 28 further supplies the clock signal CK to the decimation filter 12.
In FIG. 2, the third and fourth adders 30 and 32 are parallelly coupled to an input circuit 24 for receiving an analog input signal Sa to be digitalized. The third and fourth adders 30 and 32 are further coupled to the dither signal generator 36 for receiving a dither signal Si. Generally, a frequency of the dither signal Si is selected to a higher frequency separated from the frequency band of the analog input signal Sa. The analog input signal Sa and the ditcher signal Si are applied to the first and second .DELTA.-.SIGMA. modulation type quantizers 10a and 10b through the third and fourth adders 30 and 32, respectively. Thus, the analog input signal Sa and the dither signal Si are quantized by the first and second .DELTA.-.SIGMA. modulation type quantizers 10a and 10b. Both first and second quantized signals Sg1 and Sg2 output from the first and second .DELTA.-.SIGMA. modulation type quantizers 10a and 10b are applied to the fifth adder 34.
Either of the first and second quantized signals Sg1 and Sg2 includes two quantized components, i.e., a main quantized component Sga relating to the analog input signal Sa and a sub quantized component Sgi relating to the dither signal Si. Main quantized components Sg1a and Sg2a in the first and second quantized signals Sg1 and Sg2 have the same phase with each other. Sub quantized components Sg1i and Sg2i in the first and second quantized signals Sg1 and Sg2 have the opposite phase with each other. Thus, the main quantized components Sg1a and Sg2a emphasize each other in the fifth adder 34, but the sub quantized components Sg1i and Sg2i cancel each other in the fifth adder 34. Therefore, a combined quantization signal Sg output from the fifth adder 34 comprises only the main quantized component Sga responding the analog input signal Sa. The quantization signal Sg is emphasized twice to the each of main quantized components Sg1a and Sg2a.
The quantization signal Sg is applied to the overflow prevention filter 38. The overflow prevention filter 38 de-emphasizes the quantization signal Sg to a half, so that the emphasis of a de-emphasized quantization signal Sgo output from the overflow prevention filter 38 agrees with the each of the main quantized components Sg1a and Sg2a.
The de-emphasized quantization signal Sgo is applied to the decimation filter 12. The thin-out decimation filter 12 decimations prescribed quantization data from the de-emphasized quantization signal Sgo under the control of the clock signal CK. Thus a digital signal Sh corresponding to the analog input signal Sa is obtained from the decimation filter 12 and then applied to an output circuit 26 coupled to the decimation filter 12.
The latter conventional .DELTA.-.SIGMA. modulation A/D converter still has a drawback that the A/D converter requires at least two .DELTA.-.SIGMA. modulation type quantizers. this .DELTA.-.SIGMA. modulation A/D converter also has a drawback that the size of integrated circuit devices constituting the A/D converter thereon becomes large.